1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, more specifically to a computer automated design system and a computer automated design method for designing a semiconductor integrated circuit including orthogonal wirings and oblique wirings in a multi-level interconnect.
2. Description of the Related Art
Along with miniaturization of integrated circuits in recent years, problems with crosstalk between adjacent wires have been of concern. Especially in cases of a wire pitch of 90 nm or less, crosstalk is more likely to occur, and various technologies to suppress crosstalk have been examined.
The technologies to suppress the occurrence of crosstalk between wires include a multi-level interconnect technology using a diagonal interconnect technology. The diagonal interconnect technology utilizes “diagonal interconnect” with wires extended in directions of 45° and 135° while wires are extended in directions of 0° and 90° in “orthogonal interconnect”. Employing the diagonal interconnect technology, a wire length can be shortened by the square root of double the wire length of the orthogonal interconnect. Therefore, the wiring area can be reduced to 30% and electric power consumption can be decreased, in comparison with the orthogonal interconnect. Since the wiring area is reduced by utilizing the diagonal interconnect technology, a pitch of diagonal wires can be magnified and the design rule can be modified, in comparison with the orthogonal interconnect technology. Accordingly, crosstalk can be reduced.
However, in the multi-level interconnect technology using an diagonal interconnect technology currently used in general, a wiring layer where the diagonal routing grid is simply arranged is placed in a layer above a wiring layer where the routing grid of the orthogonal interconnect is placed. Therefore, there is a tendency that grid points of the routing grid of the orthogonal interconnect do not match grid points of the routing grid of the diagonal interconnect. When the grid points do not match each other, in placement of a via hole in a portion where wires intersect at right angle, the via hole cannot be placed at any one of adjacent points of orthogonal interconnect and diagonal interconnect. The via hole must be therefore placed at another position. The problem of displacement of the grid points becomes more obvious with increasing reduction of wire width, and the design process is complicated due to restriction of placement positions of via holes.